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Ordering number : ENN*6723
CMOS IC
LC868016/12/08A
8-Bit Single Chip Microcontroller with 16/12/08K-Byte ROM and 640-Byte RAM On Chip
Preliminary Overview
The LC868016A/12A/08A microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional blocks : - CPU : Operable at a minimum bus cycle time of 0.5s (microseconds) - On-chip ROM maximum capacity : 16K bytes - On-chip RAM capacity : 640 bytes - Dot-matrix liquid crystal display (LCD) automatic display controller / driver - External memory - 16-bit timer / counter (or two 8-bit timers) - 16-bit timer / PWM (or two 8-bit timers) - Two 8-bit synchronous serial-interface circuits - 13-source 9-vectored interrupt system All of the above functions are fabricated on a single chip.
Ver.1.12 61298
91400 RM (IM) HO No.6723-1/28
LC868016/12/08A
Features
(1) Read Only Memory (ROM) : LC868016A : LC868012A : LC868008A 16384 x 8 bits 12288 x 8 bits 8192 x 8 bits
(2) Random Access Memory (RAM)
: 512 x 8 bits (calculation area) 128 x 8 bits (display area)
(3) Bus Cycle Time / Instruction Cycle Time
Bus cycle time 0.5s 2.0s 7.5s 3.8s 183s 91.5 Instruction cycle time 1s 4s 15s 7.5s 366s 183s System clock oscillation Ceramic (CF) Ceramic (CF) Internal RC Crystal (XTAL) Oscillation frequency 12MHz 6MHz 3MHz 1.5MHz 800kHz 32.768kHz Voltage 4.5-6.0V 2.5-6.0V 2.5-6.0V 2.5-6.0V Note OCR7=0 OCR7=1 OCR7=0 OCR7=1 OCR7=0 OCR7=1 OCR7=0 OCR7=1
* Bus cycle time means ROM-read period. OCR7 : Bit-7 of the oscillation control register. (4) Ports - Input / output ports : 6 ports (47 terminals) Input/output port programmable in a nibble : 1 port (8 terminals) Input/output port programmable every function unit : 1 port (7 terminals) Input/output port programmable in a bit : 4 ports (32 terminals) - Input port : 1 port (4 terminals) - Ports at external memory mode 1. External Latch Port 0 : Address output of lower 8-bit, input/output of data Port 2 : Address output of upper 8-bit Port 5 : Bank address output 2. No External Latch Port 0 : Input/output of data Port 3 : Address output of lower 8-bit Port 2 : Address output of upper 8-bit Port 5 : Bank address output (Set whether the external latch is used or not by program.) - LCD segment driver output ports : 48 terminals (Function change available : segment/common) - LCD common driver output ports : 16 terminals (1/64 duty maximum : at using segment output ports as common output by mask option) (5) External memory access - External program memory access function External program memory capacity : 64K bytes Programable switch internal program/external program (At initial : Internal program) Enable/disable control of external program --> internal program memory switch
No.6723-2/28
LC868016/12/08A Ports Port 2 : Address output of upper 8-bit Uses EROE terminal ( OE signal of the external ROM) 1. Using the external latch Port 0 : Address output of lower 8-bit, data input port Uses the ADLC terminal (latch clock of the lower 8-bit address signal) 2. Not use the external latch Port 0 : Input port of data Port 3 : Address output of lower 8-bit - External data memory access function Using the LDC instruction External memory capacity : 16M bytes 1. Internal program memory Switch the reference of internal ROM data/external ROM data by program. 2. External program memory Reference external ROM data only. Ports Port 2 : Address output of upper 8-bit Port 5 : Bank address output Uses EROE terminal ( OE signal of the external ROM) 1. Using external latch Port 0 : Address output of lower 8-bit, input port of data Uses the ADLC terminal (latch clock of the lower 8-bit address signal) 2. Not use external latch Port 0 : Input port of data Port 3 : Address output of lower 8-bit - External RAM memory access function Using the LDX, STX instruction External memory capacity : 16M bytes Ports Port 2 : Address output of upper 8-bit Port 5 : Bank address output Uses the P46 terminal ( OE signal of external RAM) : the LDX instruction execution Uses the P47 terminal ( WE signal of external RAM) : the STX instruction execution 1. Using the external latch circuit Port 0 : Address output of lower 8-bit, input/output port of data Uses the ADLC terminal (latch clock of the lower 8-bit address signal) 2. Not use the external latch circuit Port 0 : Input/output port of data Port 3 : Address output of lower 8-bit (6) LCD automatic display controller - Display duty : 1/1 - 1/64 duty - Display bias : 1/4, 1/5, 1/7, 1/9 bias - Programmable character display / graphic display - Character display 1. On-chip character generator ROM ROM capacity : 8960 bits Character font : 5 x 7 dots Number of Characters : 256 2. LCD instruction Display : ON/OFF Cursor : ON/OFF/BLINK Character blink : ON/OFF Character scroll : Control by specified starting address
No.6723-3/28
LC868016/12/08A - Graphic display LC868000 series : 1024 dots Maximum External segment driver : Enable to extend of LCD drive - LCD contrast LCD display contrast programmable - LCD display power supply Doubler/Tripler circuit programmable Doubler voltage in the tripler mode must not be used for LCD display power supply If doubler voltage is used for LCD display power supply, the doubler mode must be selected by user program. - LCD driver Following three kinds of combination can be selected by mask option
No. 1 2 3 Segment output port 48 32 0 Common output port 16 32 64
(7) Serial-interface - Two 8-bit serial-interface circuits LSB first / MSB first function available - Internal 8-bit baud-rate generator in common with two serial-interface circuits (8) Timers - Timer0 (T0L, T0H) 16-bit timer / counter 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter - Timer1 (T1L, T1H) 16-bit timer / PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable-bit PWM (9-16 bits) - Base timer Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer clock) The Base timer clock selectable ; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of Timer 0 (9) Buzzer output - The Buzzer sound frequency selectable ; 4KHz, 2KHz (10) Remote control receiver circuit (using P73/INT3/T0IN terminal) - Noise rejection available - The interrupt polarity selectable (11) Watchdog timer - The watchdog timer is taken on RC outside. (using P70/INT0 terminal) - Watchdog timer operation selectable : interrupt system, system reset
No.6723-4/28
LC868016/12/08A (12) Interrupts system - 13-source 9-vectored interrupts : 1. External interrupt INT0 (includes watchdog timer) 2. External interrupt INT1 3. External interrupt INT2, timer / counter T0L (timer 0 lower 8 bits) 4. External interrupt INT3, base timer 5. Timer / counter T0H (timer 0 upper 8-bit) 6. Timer T1L (timer 1 lower 8-bit), Timer T1H (timer 1 upper 8-bit) 7. Serial interface SIO0 8. Serial interface SIO1 9. Port 0 or Port 3 - Interrupt priority control available Microcomputer allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can specify a low level or a high level interrupt priority from INT2/T0L through port 0 or port 3 (the above interrupt number from three through nine). It can also specify a low level or the highest level interrupt priority to INT0 and INT1. (13) Sub-routine stack levels - 128 levels (Max.) : stack area included in RAM area (14) Multiplication and division - 16 bits x 8-bit (7 instruction cycle times) - 16 bits / 8-bit (7 instruction cycle times) (15) Three oscillation circuits - On-chip RC oscillation circuit using for the system clock, for the LCD display and for the step-up circuit. - On-chip CF oscillation circuit using for the system clock and for the LCD display. - On-chip crystal oscillation circuit using for the system clock, for time-base clock and for the LCD display. (16) Standby function - HALT mode function The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This operation mode can be released by the interrupt request signals or setting to low level for the reset terminal ( RES ). - HOLD mode function The HOLD mode is used to freeze all the oscillations ; RC (internal), CF and Crystal oscillations. This mode can be released by the following operations: * Reset terminal ( RES ) set to low level. * Set to assigned level to INT0/1 terminals. * Set to assigned level to Port 0/3. (17) Factory shipment - Chip QIC160 package shipping available for sample evaluation. (18) Development support tools - Evaluation (EVA) chip - Emulator
: LC868099 : EVA86000 + ECB868000 (Evaluation chip board)
No.6723-5/28
LC868016/12/08A
Pin Assignment
EROE ADLC
CF2
CF1
VSS
XT2
XT1
RES
P27
P26
P25
P24
P23
P22
P21
P20
P07
P06
P05
P04
P03
P02
P01
P00
P37
P36
P35
P34
P33
P32
P31
P30
106
VDD P50 P51 P52 P53 P54 P55 P56 P57 P17/PWM P16/BUZ P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P47/WR P46/RD P44/FRM P43/M P42/DO P41/CL2 P40/CL1 VSS CUP1 CUP2 VOUT2 VOUT3 TEST TEST VLCD
VDD S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 36 S35
1
(X, Y) = (0, 0)
66
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
V1
V2
V3
V4
V5
No.6723-6/28
LC868016/12/08A
Pad Name and coordinates table
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Name VDD S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 Coordinates Xm -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2960 -2865 -2700 -2540 -2375 -2215 -2050 -1890 -1725 -1565 -1400 -1240 Ym 2695 2505 2345 2180 2020 1855 1695 1530 1370 1205 1045 880 720 555 395 230 70 -95 -255 -420 -580 -745 -905 -1070 -1230 -1395 -1555 -1720 -1880 -2045 -2205 -2370 -2530 -2695 -2855 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 Pad No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Name S46 S47 S48 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V1 V2 V3 V4 V5 VLCD TEST TEST VOUT3 VOUT2 CUP2 CUP1 VSS P40 P41 P42 P43 P44 P46 P47 P70 P71 P72 P73 P10 P11 P12 Coordinates Xm -1075 -915 -750 -590 -425 -265 -100 60 225 385 550 710 875 1035 1200 1360 1525 1685 1850 2055 2220 2380 2545 2705 2870 2915 2915 2820 2820 2820 2820 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 Ym -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3630 -3445 -3445 -3445 -3445 -3445 -3445 -3180 -2995 -2810 -2650 -2485 -2325 -2120 -1945 -1765 -1585 -1410 -1230 -1050 -870 -690 -525 -365 -200 -40 140 320 Pad No. 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Name P13 P14 P15 P16 P17 P57 P56 P55 P54 P53 P52 P51 P50 VDD P30 P31 P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 ADLC
EROE RES
Coordinates Xm 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 2845 2965 2800 2620 2445 2265 2085 1905 1730 1550 1370 1190 1015 835 655 475 300 120 -60 -240 -415 -595 -775 -955 -1130 -1310 -1490 -1670 -1845 -2025 -2205 -2385 -2560 -2740 Ym 500 675 855 1035 1215 1400 1580 1760 1935 2115 2295 2475 2650 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530 3530
XT1 XT2 VSS CF1 CF2
Note ; Connect the substrate of chip to VDD (or open).
No.6723-7/28
LC868016/12/08A
System Block Diagram
Interrupt Control
IR
PLA
Standby Control
ROM
RC X'tal
Clock Generator
CF
PC
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0 ALU Timer 1 Port 2
Port 3
PSW
INT0-3 Noise Rejection Filter
Port 4
RAR
XRAM 128 Bytes
Port 5
RAM
Stack Pointer CGROM
Port 0 LCD Display Controller EXT Register LCD Driver Watchdog Timer
No.6723-8/28
LC868016/12/08A
Pin Description
Name VSS VDD VLCD V1 to 5 VOUT2,3 CUP1,2 Port0 P00 to P07 No. 78,136 1,106 71 66-70 75,74 77,76 I/O I/O Function description Power terminal (-) Power terminal (+) Power terminal (-) for LCD driver Voltage supply terminals to LCD drivers Output terminals for doubler, tripler Capacitor connecting terminals for doubler, tripler *8-bit input/output port *Input/output can be specified in 4-bit *External memory mode 1. EXT resistor bit 2=0 Address output of lower 8-bit, input/output of data 2. EXT resistor bit 2=1 *Input/output of data *Input for key interrupt (P30INT=0)* *8-bit input/output port *Input/output can be specified in a bit *Another functions P10 SIO0 data output P11 SIO0 data input, bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input, bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer 1 output (PWM output) *8-bit input/output port *Input/output can be specified in a bit *External memory mode Address output of upper 8-bit *8-bit input/output port *Input/output in a bit *External memory mode 1. EXT resistor bit 2=0 : input/output port 2. EXT resistor bit 2=1 : address output of lower 8-bit for external memory *Input for key interrupt (P30INT=L)* Option *Pull-up resistor : Provided/Not provided *Output form : CMOS/N-ch open drain
115-122
Port1 P10 to P17
I/O 90-97
*Output form : CMOS/N-ch open drain
Port2 P20 to P27
I/O 123-130
*Output form : CMOS/N-ch open drain
Port3 P30 to P37
I/O 107-114
*Pull-up resistor : Provided/Not provided *Output form : CMOS/N-ch open drain
*P30INT : Bit 0 of Port 3 interrupt control register.
No.6723-9/28
LC868016/12/08A
Name Port4 P40 to P44 P46, P47 No. 79-83 84,85 I/O I/O Function description *7-bit input/output port *Input/output can be specified each upper 2 bits and lower 5 bits *Another functions P40 CL1 Latch clock P41 CL2 Shift clock P42 DO Output data P43 M Alternate signal P44 FRM Frame signal RD Read signal P46 WR Write signal P47 (P40-P44 : LCD display extend signal, P46, P47 : External RAM access signal) *8-bit input/output port *Input/output in bit unit *External memory mode 1. EXT resistor bit 3=0 : input/output 2. EXT resistor bit 3=1 : bank address output for external memory *4-bit input port *Another functions P70 INT0 input/HOLD release/N-ch Tr. output for watchdog timer P71 INT1 input/HOLD release P72 INT2 input/timer 0 event input P73 INT3 input with noise filter/timer 0 event input *Interrupt received form, vector address leading trailing leading high low & level level trailing INT0 enable enable disable enable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable Option *Pull-up resistor : Provided/Not provided *Output form : CMOS/N-ch open drain
Port5 P50 to P57
I/O 105-98
*Pull-up resistor : Provided/Not provided *Output form : CMOS/N-ch open drain
Port7 P70 to P73 86-89
I
*Pull-up resistor : Provided/Not provided
vector
03H 0BH 13H 1BH
No.6723-10/28
LC868016/12/08A
Name C1 to C16 S1 to S48
RES ADLC EROE XT1
No. 65-50 2-49 133 131 132 134 135 137 138
I/O O O I O O I O I O
Function description LCD output terminals for common LCD output terminals for segment Reset Address control signal for external memory Enable signal of external ROM output Input for 32.768kHz crystal oscillation In case of non use, connect to VDD Output for 32.768kHz crystal oscillation In case of non use, should be left unconnected Input for ceramic resonator oscillation In case of non use, connect to VDD Output for ceramic resonator oscillation In case of non use, should be left unconnected
Option LCD output terminals : segment/common -
XT2 CF1 CF2
* Port options can be specified in a bit.
* A state of port at initial
Pin name Port 0, 7 Ports 1, 2 Ports 3, 5 Port 4 Name C1 to C16 S1 to S48 Input/output mode Input Input Input Output level VDD (Display OFF) VDD (Display OFF) A state of pull-up resistor specified at pull-up option Fixed pull-up resistor exist Programmable pull-up resistor OFF Programmable pull-up resistor ON
No.6723-11/28
LC868016/12/08A 1. Absolute Maximum Ratings at VSS=0V and Ta=25C
Parameter Supply voltage Input voltage Symbol Pins Conditions Ratings VDD[V] min. -0.3 -0.3 VDD-21 VLCD-0.3 VDD-21 -0.3 -0.3 *CMOS output *At each pin Total all pins -4 typ. max. +7.0 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 mA unit V
Output voltage
Input/output voltage High Peak level output output current current Total output current Low level output current Peak output current Total output current
VDDMAX VDD VI(1) *Ports 71,72,73 * RES VI(2) VLCD VO(1) *C1 to C16 *S1 to S48 VO(2) *VOUT2,VOUT3 *CUP1,CUP2 VO(3) ADLC, EROE VIO(1) *Ports 0,1,2,3,4,5 *Port 70 IOPH(1) *Ports 0,1,2,3,4,5 *ADLC, EROE IOAH(1) *Ports 0,2,3 *C1-C16,S1-S48 *ADLC, EROE Ports 1, 4, 5 *Ports 0,1,2,3,4,5 *ADLC, EROE Port 70 Port 0 *Port 2 *ADLC, EROE Port 3 Ports 1, 5 Port 4 Port 70 C1-C16,S1-S48
-25
IOAH(2) IOPL(1) IOPL(2) IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) IOAL(6) IOAL(7) Topr
Total all pins At each pin At each pin Total all pins Total all pins Total all pins Total all pins Total all pins Total all pins Total all pins
-25 20 15 40 40 40 40 40 15 30 +70
Operating temperature range Storage temperature range
-30
C
Tstg
-55
+125
Notes : The specifications above are for a die mounted in a QIC160 type package. However, we ship this product as a die only, not a package chip. Therefore, the operational characteristics may vary depending on the user's packaging techniques.
No.6723-12/28
LC868016/12/08A 2. Recommended Operating Range at Ta=-30C to +70C, VSS=0V
Parameter Operating supply voltage range Symbol VDD(1) VDD(2) VDD(3) Hold voltage VHD VDD VDD Pins Conditions 0.98s tCYC 400s 1.9s tCYC 400s 3.9s tCYC 400s RAMs and the registers hold voltage at HOLD mode. 4.5-6.0 2.5-4.5 2.5-6.0 Ratings typ. unit V
VDD[V]
min. 4.5 4.5 2.5 2.0
max. 6.0 6.0 6.0 6.0
LCD display voltage Input high voltage
VLCD VIH(1) VIH(2)
VLCD Port 0 (Schmitt) Output disable Output disable
VIH(3)
VIH(4) VIH(5) VIL(1) VIL(2) VIL(3)
Input low voltage
VIL(4) VIL(5) tCYC FmCF(1)
*Ports 1,2,4,5 *Ports 72,73 (Schmitt) *Port 70 for Port input/interrupt *Port 71 * RES (Schmitt) Port 70 for watchdog timer Port 3 Port 0 (Schmitt) *Ports 1,2,4,5 *Ports 72,73 (Schmitt) *Port 70 Port input/interrupt *Port 71 * RES Port 70 for watchdog timer Port 3
-2VDD -VDD 0.4VDD +0.9 2.5-6.0 0.75VDD
VDD-4.5 VDD-4.5 VDD VDD
Output N-channel Tr. OFF
2.5-6.0 0.75VDD
VDD
Output N-channel Tr. OFF Output disable Output disable Output disable Output N-channel Tr. OFF
2.5-6.0
0.9VDD
VDD VDD 0.2VDD 0.25VDD 0.25VDD
2.5-6.0 0.75VDD 2.5-6.0 VSS 2.5-6.0 VSS 2.5-6.0 VSS
Output N-channel Tr. OFF Output disable
2.5-6.0 2.5-6.0 4.5-6.0 2.5-6.0 4.5-6.0
VSS VSS 0.98 3.9 11.76
Operation cycle time Oscillation frequency range (Note 1)
CF1, CF2
FmCF(2)
CF1, CF2
FmCF(3)
CF1, CF2
FmRC
FsXtal
XT1, XT2
*12MHz (ceramic resonator oscillation) *Refer to figure 1 *6MHz (ceramic resonator oscillation) *Refer to figure 1 *3MHz (ceramic resonator oscillation) *Refer to figure 1 *Internal RC oscillation Mask option is `High' *Internal RC oscillation Mask option is `Low' *32.768kHz (crystal oscillation) *Refer to figure 2
12
0.8VDD -1.0 0.25VDD 400 s 400 12.24 MHz
4.5-6.0
5.88
6
6.12
2.5-6.0
2.94
3
3.06
2.5-4.5 4.5-6.0 2.5-4.5 4.5-6.0 2.5-6.0
1.0 0.8 0.5 0.4
1.4 1.3 0.9 0.75 32.768
2.0 1.8 1.2 1.0 kHz
Continue.
No.6723-13/28
LC868016/12/08A
Parameter Oscillation stabilizing time period (Note 1)
Symbol tmsCF(1)
Pins CF1, CF2
Conditions *12MHz (ceramic resonator oscillation) *Refer to figure 3 *6MHz (ceramic resonator oscillation) *Refer to figure 3 *3MHz (ceramic resonator oscillation) *Refer to figure 3 *32.768kHz (crystal oscillation) *Refer to figure 3
Ratings VDD[V] 4.5-6.0 min. typ. 0.02 max. 0.3
unit ms
tmsCF(2)
CF1, CF2
4.5-6.0
0.02
0.3
tmsCF(3)
CF1, CF2
4.5-6.0 2.5-6.0
0.1 0.1
1 3
tssXtal
XT1, XT2
4.5-6.0 2.5-6.0
1 1
1.5 3
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6723-14/28
LC868016/12/08A 3. Electrical Characteristics at Ta=-30C to +70C, VSS=0V
Parameter Input high current Symbol IIH(1) Pins *Ports 1,2,3,4,5 *Port 0 without pull-up MOS Tr. Conditions *Output disable *Pull-up MOS Tr. OFF *VIN=VDD (including the offleak current of the output Tr.) *Output Nch Tr. OFF *VIN=VDD (including the offleak current of the output Tr.) VIN=VDD *Output disable *Pull-up MOS Tr. OFF *VIN=VSS (including the offleak current of the output Tr.) *Output Nch Tr. OFF *VIN=VSS (including the offleak current of the output Tr.) VIN=VSS IOH=-10mA IOH=-1mA IOH=-1.0mA IOH=-0.1mA IOL=10mA IOL=1.6mA *IOL=1.0mA *The current of any measurement pin is not over 1mA. IOL=1mA IOL=0.5mA VOH=0.9VDD Output disable Ratings VDD[V] 2.5-6.0 min. typ. max. 1 unit A
IIH(2)
Port 7 without pull-up MOS Tr.
2.5-6.0
1
Input low current
IIH(3) IIL(1)
RES *Ports 1,2,3,4,5 *Port 0 without pull-up MOS Tr.
2.5-6.0 2.5-6.0
1 -1
IIL(2)
Port 7 without pull-up MOS Tr.
2.5-6.0
-1
Output high voltage
IIL(3) VOH(1) VOH(2) VOH(3) VOH(4) VOL(1) VOL(2) VOL(3)
RES Port 0 of CMOS output
Output low voltage
*Ports 1,2,3,4,5 of CMOS output *ADLC, EROE *Ports 0,1,2,3,4,5 *ADLC, EROE
2.5-6.0 -1 4.5-6.0 VDD-1.5 2.5-6.0 VDD-0.4 4.5-6.0 VDD-1 2.5-6.0 VDD-0.5 4.5-6.0 4.5-6.0 2.5-6.0 1.5 0.4 0.4
V
Pull-up MOS Tr. resistor Hysteresis voltage Pin capacitance
VOL(4) VOL(5) Rpu VHIS
Port 70 *Ports 0,1,2,3,4,5 *Port 7 *Ports 0,1,2,3,4,5 *Port 7 * RES All pins
4.5-6.0 2.5-6.0 4.5-6.0 2.5-4.5 2.5-6.0
15 25
40 60 0.1VDD
0.4 0.4 70 120
k V
CP
*f=1MHz *Unmeasurement terminals for the input are set to VSS level. *Ta=25C
2.5-6.0
10
pF
No.6723-15/28
LC868016/12/08A 4. Serial Input/Output Characteristics at Ta=-30C to +70C, VSS=0V
Parameter Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Data set up time Input clock Symbol tCKCY(1) tCKL(1) tCKH(1) tCKCY(2) tCKL(2) tCKH(2) tICK *SI0,SI1 *SB0,SB1 SCK0, SCK1 *Use pull-up resistor (1k) when Nch opendrain output. *Refer to figure 5. *Data set-up to SCK0,1 *Data hold from SCK0,1 *Refer to figure 5. *Data set-up to SCK0,1 *Use pull-up resistor (1k) when Nch opendrain output. *Refer to figure 5. *Data hold from SCK0,1 *Use pull-up resistor (1k) when Nch opendrain output. *Refer to figure 5. 2.5-6.0 Pins SCK0, SCK1 Conditions Refer to figure 5. Ratings VDD[V] 2.5-6.0 min. 2 1 1 2 1/2 tCKCY 1/2 tCKCY 4.5-6.0 2.5-6.0 4.5-6.0 2.5-6.0 4.5-6.0 0.1 0.4 0.1 0.4 7/12 tCYC
+0.2
typ.
max.
unit tCYC
Serial clock
Output clock
Serial input
s
Data hold time Output delay time (Serial clock is external clock)
tCKI tCKO(1) *SO0,SO1 *SB0,SB1
2.5-6.0
7/12 tCYC
+1
Serial output
Output delay time (Serial clock is internal clock)
tCKO(2)
*SO0,SO1 *SB0,SB1
4.5-6.0
1/3 tCYC
+0.2
2.5-6.0
1/3 tCYC
+1
No.6723-16/28
LC868016/12/08A 5. Pulse Input Conditions at Ta=-30C to +70C, VSS=0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) Pins *INT0, INT1 *INT2/T0IN *Refer to figure 6 *INT3/T0IN (The noise rejection clock is selected to 1/1.) *Refer to figure 6 *INT3/T0IN (The noise rejection clock is selected to 1/16.) *Refer to figure 6 *INT3/T0IN (The noise rejection clock is selected to 1/64.) *Refer to figure 6 * RES *Refer to figure 6 Conditions *Interrupt acceptable *Timer0-countable *Interrupt acceptable *Timer0-countable Ratings VDD[V] 2.5-6.0 min. 1 typ. max. unit tCYC
2.5-6.0
2
tPIH(3) tPIL(3)
*Interrupt acceptable *Timer0-countable
2.5-6.0
32
tPIH(4) tPIL(4)
*Interrupt acceptable *Timer0-countable
2.5-6.0
128
tPIL(5)
Reset acceptable
2.5-6.0
200
s
No.6723-17/28
LC868016/12/08A 6. Current Dissipation Characteristics at Ta=-30C to +70C, VSS=0V
Parameter Current dissipation during basic operation (Note 2) Symbol IDDOP(1) Pins Conditions Ratings OCR7 VDD[V] min. 0 4.5-6.0 typ. 10 max. 25 unit mA
IDDOP(2)
IDDOP(3) IDDOP(4) IDDOP(5)
VDD *FmCF=12MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : 12MHz *Internal RC oscillation stops *FmCF=6MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : 6MHz *Internal RC oscillation stops *FmCF=3MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : 3MHz *Internal RC oscillation stops *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : RC oscillation *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : 32.768kHz *Internal RC oscillation stops Mask option is "High"
1
4.5-6.0
10
25
0 1 0
4.5-6.0 2.5-4.5
3 6 1.5
9 15 5
IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) IDDOP(13) IDDOP(14) IDDOP(15) IDDOP(16) IDDOP(17)
Mask option is "Low"
0 1 0 1 0 1 0 1 0 1 0 1
4.5-6.0 2.5-4.5 4.5-6.0 2.5-4.5 4.5-6.0 2.5-4.5
1.2 2.0 0.7 1.4 0.7 1.2 0.4 0.8 38 60 15 25
5.8 7.8 4.8 6.2 3.4 4.5 2.8 3.6 150 300 70 120
A
*OSCR : Bit 7 of the oscillation control register. Continue.
No.6723-18/28
LC868016/12/08A
Parameter
Symbol
Pins
Conditions
Ratings OCR7 VDD[V] min. 0 4.5-6.0 typ. 5.0 max. 14
unit mA
Current IDDHALT(1) VDD *HALT mode dissipation *FmCF=12MHz in HALT Ceramic resonator mode oscillation (Note 2) *FsXtal=32.768kHz crystal oscillation *System clock : 12MHz *Internal RC oscillation stops IDDHALT(2) *HALT mode *FmCF=6MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : 6MHz *Internal RC oscillation stops IDDHALT(3) *HALT mode *FmCF=3MHz IDDHALT(4) Ceramic resonator IDDHALT(5) oscillation *FsXtal=32.768kHz crystal oscillation *System clock : 3MHz *Internal RC oscillation stops *HALT mode IDDHALT(6) *FmCF=0Hz IDDHALT(7) (when oscillation IDDHALT(8) stops) IDDHALT(9) *FsXtal=32.768kHz IDDHALT(10) crystal oscillation IDDHALT(11) *System clock : IDDHALT(12) RC oscillation IDDHALT(13) IDDHALT(14) *HALT mode *FmCF=0Hz IDDHALT(15) (when oscillation IDDHALT(16) stops) IDDHALT(17) *FsXtal=32.768kHz crystal oscillation *System clock : 32.768kHz *Internal RC oscillation stops Current IDDHOLD(1) VDD HOLD mode dissipation IDDHOLD(2) in HOLD mode (Note 2)
1
4.5-6.0
5.0
14
0 1 0
4.5-6.0 2.5-4.5
2.3 4.5 0.8
7 15 4
Mask option is "High"
Mask option is "Low"
0 1 0 1 0 1 0 1 0 1 0 1
4.5-6.0 2.5-4.5 4.5-6.0 2.5-4.5 4.5-6.0 2.5-4.5
650 1000 340 600 400 600 200 350 25 36 8 12
2700 4200 2200 2500 1600 2400 1300 1500 100 140 55 85
A
4.5-6.0 2.5-4.5
0.05 0.02
30 20
(Note 2) The currents of the output transistors, pull-up transistors and the LCD bleeder resistors are ignored. Refer to figure 7.
No.6723-19/28
LC868016/12/08A 7. LCD Voltage and LCD Driver Characteristics at Ta=-30C to +70C, VSS=0V
Parameter VDD-Ci drop voltage (i : 1 to 16) VX-Ci drop voltage (X : 1 to 4) (i : 1 to 16) VX-Ci drop voltage (X : 1 to 5) (i : 1 to 16) VDD-Si drop voltage (i : 1 to 48) VX-Si drop voltage (X : 1 to 4) (i : 1 to 48) VX-Si drop voltage (i : 1 to 5) (i : 1 to 48) V1 output voltage V2 output voltage V3 output voltage V4 output voltage LCD display current Symbol |VD1| |VD2| Pins, Conditions *Only a Ci terminal for -15A *LCD display ON *1/5 bias *V5=0V *Only a Ci terminal for +15A *LCD display ON *1/5 bias *V5=0V *Only a Si terminal for -15A *LCD display ON *1/5 bias *V5=0V *Only a Ci terminal for +15A *LCD display ON *1/5 bias *V5=0V *LCD clock frequency=0Hz *LCD display ON *1/5 bias *V5=0V *Refer to figure 9 Ratings typ. unit mV
VDD[V] 2.9 5.0 2.9 5.0 2.9 5.0
min.
max. 120 200 120 200
|VD3|
-120 -200
|VD4| |VD5|
2.9 5.0 2.9 5.0 2.9 5.0 -120 -200
120 200 120 200
|VD6|
VV1 VV2 VV3 VV4 ILCD1 ILCD2
Step up voltage
VOUT2
VOUT3
Contrast current (VLCD terminal)
ILC1 ILC2 ILC3 ILC4 ILC5
*LCD display ON *1/5 bias *VLCD=0V *V1-V5 are opened *Refer to figure 8 *V1-V5 resistor=20k *LCD display ON *LVCR0=1 (doubler) *VOUT2 *C5=C6=0.1F *Internal RC oscillation start *Refer to figure 10 *V1-V5 resistor=20k *LCD display ON *LVCR0=0 (tripler) *VOUT3 *C5=C6=0.1F *Internal RC oscillation start *Refer to figure 11 *LCD display ON *V5=0V *VLCD=-3V *Refer to figure 12
20k mode 4k mode IL=100A
2.9 5.0 2.9 5.0 2.9 5.0 2.9 5.0 5 2.9 5 2.9 2.7 3 5 2.7 3 5
0.75VDD 0.80VDD 0.85VDD 0.55VDD 0.60VDD 0.65VDD 0.35VDD 0.40VDD 0.45VDD 0.15VDD 0.20VDD 0.25VDD 25 15 125 75 -2.7 -3 -5 -2.7 -3 -5 50 29 250 150 -1.9 -2.8 -4.8 -1.8 -2.6 -4.6 100 60 500 300 -1.7 -2.6 -4.5 -1.5 -2.2 4.2
V
A
V
IL=500A
IL=100A IL=500A
5 5
-10 -10
-9.4 -8.5
-9.0 -7.5
VCCR=1 VCCR=2 VCCR=4 VCCR=8 VCCR=10H
5 5 5 5 5
5 2.5 1.25 0.6 0.3
10 5 2.5 1.25 0.6
20 10 5 2.5 1.25
mA
A
VCCR : The LCD contrast control register LVCR0 : Bit 0 of the LCD bias control register
No.6723-20/28
LC868016/12/08A Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type 12MHz ceramic resonator oscillation 6MHz ceramic resonator oscillation Maker Murata Kyocera Murata Kyocera 3MHz ceramic resonator oscillation Murata Kyocera Oscillator CSA12.0MT CST12.00MTW KBR-12.0M CSA6.00MG CST6.00MGW KBR-6.0MSA KBR-6.0MKS CSA3.0MG CST3.0MGW KBR-3.0MS C1 C2 33pF 33pF on chip 33pF 33pF 33pF 33pF on chip 33pF 33pF on chip 33pF 33pF on chip 47pF 47pF
* Both C1 and C2 must use K rank (10%) and SL characteristics. Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type 32.768kHz crystal oscillation Maker CITIZEN SII Oscillator CFS-308 DT-VT-200 C3 18pF 18pF C4 18pF 18pF
* Both C3 and C4 must use J rank (5%) and CH characteristics. (It is about the application which is not in need of high precision. Use K rank (10%) and SL characteristics.)
(Notes)
*Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. *For other oscillators, please request an evaluation of microcomputer and oscillator matching to the oscillator manufacturer.
CF1
CF2
XT1
XT2
X'tal CF C1 C2 C3 C4
Figure 1
Ceramic oscillation circuit
Figure 2
Crystal oscillation circuit
No.6723-21/28
LC868016/12/08A
Power supply
Reset time
VDD VDD limit 0V
RES
Internal RC oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unstable
Reset
Execution of instructions
Reset time and oscillation stable time
HOLD release signal
Valid
Internal RC oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Execution of instructions
HOLD release signal and oscillation stable time
Figure 3
Oscillation stable time
No.6723-22/28
LC868016/12/08A
VDD
RRES
RES CRES
(Note) Fix the value of CRES, RRES that is sure to reset until 200s, after Power supply has been over inferior limit of supply voltage. Figure 4 Reset circuit
0.5VDD
tCKCY tCKL SCK0 SCK1 tICK SI0 SI1 tCKO SO0, SO1 SB0, SB1 50pF tCKI tCKH
VDD
1k

Figure 5
Serial input / output test condition
tPIL
tPIH
Figure 6
Pulse input timing condition
No.6723-23/28
LC868016/12/08A
VDD A VDD Open CUP1 CUP2 VOUT2 VOUT3 CF1 CF2 VSS XT1 V5 VLCD XT2 V1 Open VDD V1 CUP1 CUP2 VOUT2 VOUT3 CF1 CF2 VSS XT1 V5 VLCD XT2 Open VDD
A
VSS
VSS
Figure 7
Current dissipation measurement
Figure 8
LCD display current measurement
VDD
VDD
VDD CUP1 CUP2 Open VOUT2 VOUT3 VLCD CF1 CF2 VSS XT1 XT2
IL
V1
VDD V1 CUP1 CUP2 VOUT2 VOUT3 CF1 CF2 VSS XT1 V5 VLCD XT2 Open
V4 V5
V
V
VSS
VSS
*VOUT3 FOpen
Figure 9
Output voltage of V1-V4 measurement
Figure 10
Step up output voltage measurement (1)
VDD
VDD
VDD C5 C6 C7 IL CF1 CF2 VSS XT1 XT2 V1 CUP1 CUP2 VOUT2 VOUT3 V5 VLCD Open
VDD V1 CUP1 CUP2 VOUT2 VOUT3 CF1 CF2 VSS XT1 V4 V5 VLCD XT2 Open
V
A
VSS
VSS
-3V
Figure 11
Step up output voltage measurement (2)
Figure 8
Contrast current measurement
No.6723-24/28
LC868016/12/08A 8. AC Characteristics at Ta=-30C to +70C, VSS=0V Load capacity : 100pF (Port 0, ADLC, EROE ) Load capacity : 80pF (Output terminals except above) *tCLCL=1/12 tCYC
External program memory timing
Parameter ADLC pulse width Address settling time Address hold time ADLC ! control signal EROE pulse width Data delay time Data hold time
EROE ! address in
Symbol tLHLL tAVLL tLLAX tLLEL tELEH tELIV tEHIX tEHAV
Pads and Conditions
Ratings VDD[V] 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 min. 2tCLCL-40 2tCLCL-160 tCLCL-40 tCLCL-160 tCLCL-35 tCLCL-140 tCLCL-25 tCLCL-100 3tCLCL-35 3tCLCL-140 3tCLCL-125 3tCLCL-400 0 0 tCLCL-8 tCLCL-32 max.
unit ns
For ADLC For ADLC For EROE
From EROE For EROE
Refer to figure 13.
1 tCYC SCLK tLHLL ADLC tLLEL tELEH EROE tELIV tEHAV tLLAX tAVLL tEHIX IR A7-A0 tCLCL
Port 0
A7-A0
Port 2
A15-A8
A15-A8
Port 3
A7-A0
A7-A0
EROE
Port 0
A7-A0
DATA
Port 2
A15-A8
Port 3
A7-A0
Port 5
Bank
Figure 13
Timing of the external Program Memory/Data Memory
No.6723-25/28
LC868016/12/08A External data memory timing
Parameter
RD pulse width WR pulse width
Symbol tRLRH tWLWH tLLAX
Pads and Conditions
Data address hold time
For ADLC (at LDX) For ADLC (at STX)
Data delay time Data hold time Data floating time Data address setting time ADLC ! control signal
tRLDV tRHDX tRHDZ tAVLL tLLRL tLLWL
From RD From RD From RD For ADLC For RD For WR For WR
Data settling time Data in WR =1 Data hold time Control signal ! ADLC
tQVWL tQVWH tWHQX tRHLH tWHLH
From WR For RD For WR
VDD[V] 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0
Ratings min. max. 6tCLCL-80 6tCLCL-320 6tCLCL-80 6tCLCL-320 2tCLCL-35 2tCLCL-140 2tCLCL-35 2tCLCL-140 5tCLCL-125 5tCLCL-400 0 0 2tCLCL-70 2tCLCL+70 2tCLCL-280 2tCLCL+280 tCLCL-40 tCLCL-160 3tCLCL-50 3tCLCL+50 3tCLCL-200 3tCLCL+200 3tCLCL-50 3tCLCL+50 3tCLCL-200 3tCLCL+200 tCLCL-60 tCLCL-240 7tCLCL-140 7tCLCL-560 tCLCL-50 tCLCL-200 tCLCL-50 tCLCL+50 tCLCL-200 tCLCL+200 tCLCL-50 tCLCL+50 tCLCL-200 tCLCL+200
unit ns
Refer to figure 14.
tCLCL 1 tCYC
SCLK
ADLC
EROE
tLLRL tRLDV
tRLRH
tRHLH
RD tRHDZ tAVLL tLLAX tRHDX DATA tLLWL WR tLLAX (at writing) Port 0 A7-A0 tQVWL DATA tQVWH Port 2 A15-A8 tWHQX tWLWH Z tWHLH (at reading) Port 0 A7-A0
Port 5
Bank
Port 3
A7-A0
Figure 14
Timing of the external RAM
No.6723-26/28
LC868016/12/08A * Evaluation Sample (ES) The factory shipment of this microcomputer is chip. But there are two types of shipment of evaluation sample. One type is chip and the other is package (QIC160). If you selected package type, please refer to the following pin assignment and layout, and make the user target board. * Pin Assignment of evaluation sample (Package type)
90
115
110
100
85
P10 P73 P72 P71 P70 P47 P46 P44 P43 P42 P41 P40 VSS CUP1 CUP2 VOUT2 VOUT3
P50
P51
P52 P53 P54
P55 P56 P57 P17
P16
P15 P14 P13 P12
P11
VLCD VDD P30 P31 P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 ADLC EROM RES XT1 XT2 VSS CF1 CF2 V5 V4 V3 V2 V1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36
125 75
130 70
140
LC868016-QIC160
60
150 50
155 45
10
20
30
VDD
S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34
S1 S2 S3 S4 S5 S6 S7 S8
35
1
S35
No.6723-27/28
LC868016/12/08A * Layout of evaluation sample (Package type) : QIC160
PS No.6723-28/28

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